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MC14046B Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators, a voltage-controlled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs, PCAin and PCBin. Input PCAin can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1out, and maintains 90 phase shift at the center frequency between PCAin and PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2 out and LD, and maintains a 0 phase shift between PCA in and PCBin signals (duty cycle is immaterial). The linear VCO produces an output signal VCO out whose frequency is determined by the voltage of input VCO in and the capacitor and resistors connected to pins C1A, C1B, R1, and R2. The source-follower output SFout with an external resistor is used where the VCO in signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control.
Features
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PDIP-16 P SUFFIX CASE 648 16 MC14046BCP AWLYYWWG 1 16 SOIC-16 DW SUFFIX CASE 751G 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator MC14046B ALYWG 14046BG AWLYYWW
* * * * * * *
Buffered Outputs Compatible with MHTL and Low-Power TTL Diode Protection on All Inputs Supply Voltage Range = 3.0 to 18 V Pin-for-Pin Replacement for CD4046B Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle Limited Pb-Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin Iin PD TA Tstg Parameter DC Supply Voltage Range Input Voltage Range (All Inputs) DC Input Current, per Pin Power Dissipation, per Package (Note 1) Operating Temperature Range Storage Temperature Range Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 Unit V V mA mW C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C
(c) Semiconductor Components Industries, LLC, 2005
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Publication Order Number: MC14046B/D
1
August, 2005 - Rev. 10
MC14046B
BLOCK DIAGRAM
PCAin 14 PCBin 3 VCOin 9 VDD = PIN 16 VSS = PIN 8 INH 5 VSS SELF BIAS CIRCUIT PHASE COMPARATOR 1 PHASE COMPARATOR 2 VOLTAGE CONTROLLED OSCILLATOR (VCO) SOURCE FOLLOWER 2 PC1 out 13 PC2 out 1 LD 4 11 12 6 7 VCO out R1 R2 C1 A C1 B
PIN ASSIGNMENT
LD PC1out PCBin VCOout INH C1A C1B VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD ZENER PCAin PC2out R2 R1 SFout VCOin
10 SF out 15 ZENER
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 15 - Min - - - - 55_C 25_C Typ 0 0 0 125_C Max Min - - - Max Min - - - Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 - - - 0.05 0.05 0.05 - - - 0.05 0.05 0.05 - - - "1" Level VOH Vin = 0 or VDD 4.95 9.95 14.95 - - - 4.95 9.95 14.95 - - - 5.0 10 15 4.95 9.95 14.95 - - - Vdc Input Voltage (Note 2) (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) "0" Level VIL Vdc 1.5 3.0 4.0 - - - - - - - - - - 2.25 4.50 6.75 2.75 5.50 8.25 1.5 3.0 4.0 - - - - - - - - - - 1.5 3.0 4.0 - - - - - - - - - - "1" Level VIH 3.5 7.0 11 3.5 7.0 11 3.5 7.0 11 Vdc Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH mAdc Source - 1.2 - 0.25 - 0.62 - 1.8 0.64 1.6 4.2 - - - - - - 1.0 - 0.2 - 0.5 - 1.5 0.51 1.3 3.4 - - - - - - 1.7 - 0.36 - 0.9 - 3.5 0.88 2.25 8.8 - 0.7 - 0.14 - 0.35 - 1.1 0.36 0.9 2.4 - - - - - Sink IOL mAdc Input Current Iin 0.1 - 5.0 10 20 0.00001 5.0 0.005 0.010 0.015 0.1 7.5 5.0 10 20 1.0 - 150 300 600 mAdc pF mAdc Input Capacitance Cin Quiescent Current (Per Package) Inh = PCAin = VDD, Zener = VCOin = 0 V, PCBin = VDD or 0 V, Iout = 0 mA Total Supply Current (Note 3) (Inh = "0", fo = 10 kHz, CL = 50 pF, R1 = 1.0 MW, R2 = R RSF = , and 50% Duty Cycle) IDD 5.0 10 15 5.0 10 15 IT IT = (1.46 mA/kHz) f + IDD IT = (2.91 mA/kHz) f + IDD IT = (4.37 mA/kHz) f + IDD mAdc 2. Noise immunity specified for worst-case input combination. Noise Margin for both "1" and "0" level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc 3. To Calculate Total Current in General: VCOin - 1.65 VDD - 1.35 3/4 VCOin - 1.65 3/4 IT [ 2.2 x VDD + + 1.6 x + 1 x 10-3 (CL + 9) VDD f + R1 R2 RSF 1 x 10-1 VDD2 100% Duty Cycle of PCAin 100 + IQ where: IT in mA, CL in pF, VCOin, VDD in Vdc, f in kHz, and R1, R2, RSF in MW, CL on VCOout.
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4. The formula given is for the typical characteristics only. ZENER DIODE SOURCE-FOLLOWER VOLTAGE CONTROLLED OSCILLATOR (VCO) PHASE COMPARATORS 1 and 2
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25C)
Dynamic Resistance (Iz = 1.0 mA)
Zener Voltage (Iz = 50 mA)
Linearity (VCOin = 2.5 V 0.3 V, RSF > 50 kW) (VCOin = 5.0 V 2.5 V, RSF > 50 kW) (VCOin = 7.5 V 5.0 V, RSF > 50 kW)
Offset Voltage (VCOin minus SFout, RSF > 500 kW)
Input Resistance - VCOin
Output Duty Cycle
Linearity (R2 = ) (VCOin = 2.5 V 0.3 V, R1 > 10 kW) (VCOin = 5.0 V 2.5 V, R1 > 400 kW) (VCOin = 7.5 V 5.0 V, R1 1000 kW)
Temperature - Frequency Stability (R2 = )
Maximum Frequency (VCOin = VDD, C1 = 50 pF R1 = 5.0 kW, and R2 = )
DC Coupled - PCAin, PCBin
Minimum Input Se-sitivity AC Coupled -- PCAin C series = 1000 pF, f = 50 kHz
Input Resistance - PCAin
Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns
Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns
- PCBin
Characteristic
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MC14046B
Symbol
fmax
tTHL
tTLH
Rin
Rin
Rin
Vin
RZ
VZ
-
-
-
-
-
-
3 5 to 15 5 to 15 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 - - Minimum Device 150 150 6.7 0.5 1.0 1.4 1.0 0.2 0.1 - - - - - - - - - - - - - - - - - - - - - - - See Noise Immunity Typical 0.12 0.04 0.015 1500 1500 1.65 1.65 1.65 100 200 400 700 100 50 37 180 90 65 7.0 0.1 0.6 0.8 1.0 1.0 1.0 0.7 1.4 1.9 2.0 0.4 0.2 50 MaximumIII Device 300 600 1050 175 75 55 350 150 110 7.3 2.2 2.2 2.2 - - - - - - - - - - - - - - - - - - - mV p-p Units %/_C MHz MW MW MW ns ns % % % W V V
MC14046B
ORDERING INFORMATION
Device MC14046BCP MC14046BCPG MC14046BDW MC14046BDWG MC14046BDWR2 MC14046BDWR2G MC14046BF MC14046BFEL MC14046BFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 WB SOIC-16 WB (Pb-Free) SOIC-16 WB SOIC-16 WB (Pb-Free) SOEIAJ-16 SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 500 Units / Rail 500 Units / Rail 47 Units / Rail 47 Units / Rail 1000 Units / Tape & Reel 1000 Units / Tape & Reel 50 Units / Rail 2000 Units / Tape & Reel 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC14046B
PHASE COMPARATOR 1
Input Stage 00 XX 11 PCAin PCBin 0 1 10 01
PC1out
PHASE COMPARATOR 2
Input Stage XX PCAin PCBin 01 11
00 10 10
00 01 11 01
00 10 11
PC2out LD (Lock Detect) Refer to Waveforms in Figure 3.
0 0
3-State Output Disconnected 1
1 0
Figure 1. Phase Comparators State Diagrams
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Characteristic Using Phase Comparator 1 Using Phase Comparator 2 No signal on input PCAin. VCO in PLL system adjusts to center frequency (f0). VCO in PLL system adjusts to minimum frequency (fmin). Phase angle between PCAin and PCBin. 90 at center frequency (f0), approaching 0_ and 180 at ends of lock range (2fL) Yes Always 0_ in lock (positive rising edges). Locks on harmonics of center frequency. Signal input noise rejection. Lock frequency range (2fL). No High Low The frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2fL = full VCO frequency range = fmax - fmin. Capture frequency range (2fC). The frequency range of the input signal on which the loop will lock if it was initially out of lock. Depends on low-pass filter characteristics (see Figure 3). fC v fL fC = fL Center frequency (f0). The frequency of VCOout, when VCOin = 1/2 VDD fmin = 1 VCO output frequency (f). R2(C1 + 32 pF) 1 (VCO input = VSS) Note: These equations are intended to be a design guide. Since calculated component values may be in error by as much as a factor of 4, laboratory experimentation may be required for fixed designs. Part to part frequency variation with identical passive components is typically less than 20%. fmax = R1(C1 + 32 pF) + fmin (VCO input = VDD) Where: 10K v R1 v 1 M 10K v R2 v 1 M 100pF v C1 v .01 mF
Figure 2. Design Information http://onsemi.com
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MC14046B
9 VCOin PCAin @ FREQUENCY f PCBin 14 3 PHASE 2 OR 13 COMPARATOR PC1out OR PC2out EXTERNAL LOW-PASS FILTER 9 11 R1 EXTERNAL /N COUNTER R2 12 SOURCE FOLLOWER 10 RSF 4 CIA CI 7 CIB VCOout @ FREQUENCY Nf = f SFout
VCO 6
Typical Low-Pass Filters
(a) INPUT R3 C2 OUTPUT 2fC [ 1 p 2 p fL R3 C2 (a) INPUT R3 R4 C2 Typically: OUTPUT N R4 C2 + 6N - fmax 2 p D f (R3 ) 3, 000W) C2 + 100NDf - R4 C2 fmax2 D f = fmax - fmin NOTE: Sometimes R3 is split into two series resistors each R3 / 2. A capacitor CC is then placed from the midpoint to ground. The value for CC should be such that the corner frequency of this network does not significantly affect Wn. In Figure B, the ratio of R3 to R4 sets the damping, R4 ^ (0.1)(R3) for optimum results.
LOW-PASS FILTER
Filter A Definitions: N = Total division ratio in feedback loop K = VDD/ for Phase Comparator 1 K = VDD/4 for Phase Comparator 2 2 p D fVCO KVCO + VDD - 2 V 2 p fr (at phase detector input) for a typical design Wn ^ 10 ^ 0.707 wn + KfKVCO NR3C2 wn + Filter B KfKVCO NC2(R3 ) R4) N ) KfKVCO
z+
Nwn 2KfKVCO 1 R3C2S ) 1
z + 0.5 wn (R3C2 ) F(s) +
F(s) +
R3C2S ) 1 S(R3C2 ) R4C2) ) 1
Waveforms Phase Comparator 1
PCAin VDD VSS VOH VOL VOH VOL VOH VOL PCAin
Phase Comparator 2
VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL
PCBin PC1out VCOin
PCBin LD PC2out VCOin
Note: (1) (2) (3) (4)
for further information, see: F. Gardner, "Phase-Lock Techniques", John Wiley and Son, New York, 1966. G. S. Moschytz, "Miniature RC Filters Using Phase-Locked Loop", BSTJ, May, 1965. Garth Nash, "Phase-Lock Loop Design Fundamentals", AN-535, Motorola Inc. A. B. Przedpelski, "Phase-Locked Loop Design Articles", AR254, reprinted by Motorola Inc.
Figure 3. General Phase-Locked Loop Connections and Waveforms
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MC14046B
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 WB DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-03 ISSUE C
D
16 M 9
A
q
h X 45_
0.25
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
M
B
8X
1
8
16X
B TA
S
0.25
M
B
S
A
E B
A1
14X
e
SEATING PLANE
T
C
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L
MC14046B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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